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LM5041 cascaded pwm controller general description the LM5041 pwm controller contains all of the features necessary to implement either current-fed or voltage-fed push-pull or bridge power converters. these ?cascaded? topologies are well suited for multiple output and higher power applications. the LM5041?s four control outputs in- clude: the buck stage controls (hd and ld) and the push- pull control outputs (push and pull). push-pull outputs are driven at 50% nominal duty cycle at one half of the switching frequency of the buck stage and can be configured for either a guaranteed overlap time (for current-fed applications) or a guaranteed both-off time (for voltage-fed applications). push-pull stage mosfets can be driven directly from the internal gate drivers while the buck stage requires an exter- nal driver such as the lm5102. the LM5041 includes a high-voltage start-up regulator that operates over a wide input range of 15v to 100v. the pwm controller is designed for high-speed capability including an oscillator frequency range up to 1 mhz and total propagation delays of less than 100ns. additional features include: line under-voltage lock- out (uvlo), soft-start, an error amplifier, precision voltage reference, and thermal shutdown. features n internal start-up bias regulator n programmable line under-voltage lockout (uvlo) with adjustable hysteresis n current mode control n internal error amplifier with reference n dual mode over-current protection n leading edge blanking n programmable push-pull overlap or dead time n internal 1.5a push-pull gate drivers n programmable soft-start n programmable oscillator with sync capability n precision reference n thermal shutdown applications n telecommunication power converters n industrial power converters n multi-output power converters n +42v automotive systems packages n tssop-16 n llp-16 (5x5 mm) thermally enhanced typical application circuit 20074901 simplified cascaded push-pull power converter august 2003 LM5041 cascaded pwm controller ? 2003 national semiconductor corporation ds200749 www.national.com
connection diagram 20074902 16-lead tssop, llp ordering information order number package type nsc package drawing supplied as LM5041mtc tssop-16 mtc-16 92 units per anti-static tube LM5041mtcx tssop-16 mtc-16 2500 units on tape and reel LM5041sd llp-16 sda-16a available soon LM5041sdx llp-16 sda-16a available soon pin description pin name description application information 1v in source input voltage input to start-up regulator. input range 15v to 100v. 2 fb feedback signal inverting input for the internal error amplifier. the non-inverting input is connected to a 0.75v reference. 3 comp output of the internal error amplifier there is an internal 5k ? resistor pull-up on this pin. the error amplifier provides an active sink. 4 ref precision 5 volt reference output maximum output current: 10ma. locally decouple with a 0.1f capacitor. reference stays low until the line uv and the v cc uv are satisfied. 5 hd main buck pwm control output buck switch pwm control output. the maximum duty cycle clamp for this output corresponds to an off time of typically 240ns per cycle. the lm5101 or lm5102 buck stage gate driver can be used to level shift and drive the buck switch. 6 ld sync switch control output sync switch control output. inversion of hd output. the lm5101 or lm5102 lower drive can be used to drive the synchronous rectifier switch. 7v cc output from the internal high voltage start-up regulator. regulated to 9 volts. if an auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal start-up regulator will shutdown, reducing the ic power dissipation. 8 push output of the push-pull drivers output of the push-pull gate driver. output capability of 1.5a peak . LM5041 www.national.com 2
pin description (continued) pin name description application information 9 pull output of the push-pull drivers output of the push-pull gate driver. output capability of 1.5a peak. 10 pgnd power ground connect directly to analog ground. 11 agnd analog ground connect directly to power ground. 12 cs current sense input current sense input to the pwm comparator (cm control). there is a 50ns leading edge blanking on this pin. using separate dedicated comparators, if cs exceeds 0.5v the outputs will go into cycle by cycle current limit. if cs exceeds 0.6v the outputs will be disabled and a soft-start commenced. 13 ss soft-start control an external capacitor and an internal 10ua current source, set the soft-start ramp. the controller will enter a low power state if the ss pin is below the shutdown threshold of 0.45v 14 time push-pull overlap and dead time control an external resistor sets the overlap time or dead time for the push-pull outputs. a resistor connected between time and gnd produces overlap. a resistor connected between time and ref produces dead time. 15 rt / sync oscillator timing resistor pin and sync an external resistor sets the oscillator frequency. this pin will also accept an external oscillator. 16 uvlo line under-voltage shutdown an external divider from the power converter source sets the shutdown levels. threshold of operation equals 2.5v. hysteresis is set by a switched internal current source (20a). LM5041 www.national.com 3
block diagram simplified block diagram 20074903 LM5041 www.national.com 4
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. v in to gnd 100v v cc to gnd 16v all other inputs to gnd -0.3 to 7v junction temperature 150?c storage temperature range -65?c to +150?c esd rating 2 kv lead temperature (note 2) wave 4 seconds 260?c infrared 10 seconds 240?c vapor phase 75 seconds 219?c operating ratings (note 1) v in 15 to 90v junction temperature -40?c to +105?c electrical characteristics specifications with standard typeface are for t j = 25?c, and those with boldface type apply over full operating junction temperature range .v in = 48v, v cc = 10v, rt = 26.7k ? ,r set = 20k ? ) unless otherwise stated (note 3) symbol parameter conditions min typ max units startup regulator v cc reg v cc regulation open circuit 8.7 9 9.3 v v cc current limit (note 4) 15 25 ma i-v in startup regulator leakage (external vcc supply) v in = 100v 145 500 a shutdown current (iin) uvlo = 0v, v cc = open 350 450 a v cc supply v cc under-voltage lockout voltage (positive going v cc ) v cc reg - 400mv v cc reg - 275mv v v cc under-voltage hysteresis 1.7 2.1 2.6 v supply current (i cc )c l =0 3 4 ma error amplifier gbw gain bandwidth 3 mhz dc gain 80 db input voltage v fb = comp 0.735 0.75 0.765 v comp sink capability v fb = 1.5v, comp= 1v 4 8ma reference supply v ref ref voltage i ref =0ma 4.85 5 5.15 v ref voltage regulation i ref = 0 to 10ma 25 50 mv ref current limit 15 20 ma current limit ilim delay to output cs step from 0 to 0.6v time to onset of out transition (90%) c l =0 40 ns cycle by cycle threshold voltage 0.45 0.5 0.55 v cycle skip threshold voltage resets ss capacitor; auto restart 0.55 0.6 0.65 v leading edge blanking time 50 ns cs sink current (clocked) cs = 0.3v 25 ma LM5041 www.national.com 5
electrical characteristics (continued) specifications with standard typeface are for t j = 25?c, and those with boldface type apply over full operating junction temperature range .v in = 48v, v cc = 10v, rt = 26.7k ? ,r set = 20k ? ) unless otherwise stated (note 3) symbol parameter conditions min typ max units soft-start soft-start current source 7 10 13 a soft-start to comp offset 0.35 0.55 0.75 v shutdown threshold 0.25 0.5 0.75 v oscillator frequency1 (rt = 26.7k ? ) t j = 25?c 180 175 200 220 225 khz frequency2 (rt = 7.87k ? ) 515 600 685 khz sync threshold 3 3.5 v pwm comparator delay to output comp set to 2v cs stepped 0 to 0.4v, time to onset of out transition low 25 ns max duty cycle ts = oscillator period (ts-240ns)/ts) % min duty cycle comp = 0v 0 % comp to pwm comparator gain 0.32 comp open circuit voltage fb=0v 4.1 4.8 5.5 v comp short circuit current fb = 0v, comp = 0v 0.6 1 1.4 ma slope compensation slope comp amplitude delta increase at pwm comparator to cs 110 mv uvlo shutdown under-voltage shutdown 2.44 2.5 2.56 v under-voltage shutdown hysteresis current source 16 20 24 a buck stage outputs output high level 5 (v ref )v output high saturation i out = 10ma ref=v out 0.5 1 v output low saturation i out = ?10ma 0.5 1 v rise time c l = 100pf 10 ns fall time c l = 100pf 10 ns push-pull outputs overlap time r set = 20k ? connected to gnd, 50% to 50% transitions 60 90 120 ns dead time r set = 20k ? connected to gnd, 50% to 50% transitions 65 95 125 ns LM5041 www.national.com 6
electrical characteristics (continued) specifications with standard typeface are for t j = 25?c, and those with boldface type apply over full operating junction temperature range .v in = 48v, v cc = 10v, rt = 26.7k ? ,r set = 20k ? ) unless otherwise stated (note 3) symbol parameter conditions min typ max units output high saturation i out = 50ma v cc -v out 0.25 0.5 v output low saturation i out = 100ma 0.5 1 v rise time c l = 1nf 20 ns fall time c l = 1nf 20 ns thermal shutdown t sd thermal shutdown temp. 165 ?c thermal shutdown hysteresis 25 ?c thermal resistance ja junction to ambient mtc package 125 ?c/w sda package 32 ?c/w note 1: absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions under which operation of the device is intended to be functional. for guaranteed specifications and test conditions, see the electrical characteristics. note 2: for detailed information on soldering plastic tssop and llp packages, refer to the packaging data book available from national semiconductor corporation. note 3: all limits are guaranteed. all electrical characteristics having room temperature limits are tested during production with t a =t j = 25?c. all hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. note 4: device thermal limitations may limit usable range. LM5041 www.national.com 7
typical performance characteristics v cc and v in vs v in v cc vs i cc 20074908 20074909 ss pin current vs temp frequency vs rt 20074915 20074910 overlap time vs r set dead time vs r set 20074911 20074912 LM5041 www.national.com 8
typical performance characteristics (continued) overlap time vs temp dead time vs temp 20074913 20074914 error amplifier gain phase 20074916 LM5041 www.national.com 9
detailed operating description the LM5041 pwm controller contains all of the features necessary to implement either current-fed or voltage-fed push-pull or bridge power converters. these ?cascaded? topologies are well suited for multiple output and higher power applications. the LM5041?s four control outputs in- clude: the buck stage controls (hd and ld) and the push- pull control outputs (push and pull). push-pull outputs are driven at 50% nominal duty cycle at one half of the switching frequency of the buck stage and can be configured for either a guaranteed overlap time (for current-fed applications) or a guaranteed both-off time (for voltage-fed applications). push-pull stage mosfets can be driven directly from the internal gate drivers while the buck stage requires an exter- nal driver such as the lm5102. the LM5041 includes a high-voltage start-up regulator that operates over a wide input range of 15v to 100v. the pwm controller is designed for high-speed capability including an oscillator frequency range up to 1 mhz and total propagation delays of less than 100ns. additional features include: line under-voltage lock- out (uvlo), soft-start, an error amplifier, precision voltage reference, and thermal shutdown. high voltage start-up regulator the LM5041 contains an internal high-voltage start-up regu- lator, thus the input pin (vin) can be connected directly to the line voltage. the regulator output is internally current limited to 15ma. when power is applied, the regulator is enabled and sources current into an external capacitor connected to the vcc pin. the recommended capacitance range for the vcc regulator is 0.1uf to 100uf. when the voltage on the vcc pin reaches the regulation point of 9v and the internal voltage reference (ref) reaches its regulation point of 5v, the controller outputs are enabled. the buck stage outputs will remain enabled until vcc falls below 7v or the line under-voltage lockout detector indicates that vin is out of range. the push-pull outputs continue switching until the ref pin voltage falls below approximately 3v. in typical applications, an auxiliary transformer winding is connected through a diode to the vcc pin. this winding must raise the vcc voltage above 9.3v to shut off the internal start-up regulator. powering v cc from an auxiliary winding improves efficiency while reducing the controller?s power dissipation. the recommended capacitance range for the vref regulator output is 0.1uf to 10uf. the external v cc capacitor must be sized such that the capacitor maintains a v cc voltage greater than 7v during the initial start-up. during a fault mode when the converter aux- iliary winding is inactive, external current draw on the v cc line should be limited so the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller. an external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the v cc and the v in pins together and feeding the external bias voltage into the two pins. line under-voltage detector the LM5041 contains a line under-voltage lockout (uvlo) circuit. an external set-point resistor divider from v in to ground sets the operational range of the converter. the divider must be designed such that the voltage at the uvlo pin will be greater than 2.5v when v in is in the desired operating range. if the under-voltage threshold is not met, all functions of the controller are disabled and the controller will enter a low-power state with input current < 300a. ulvo hysteresis is accomplished with an internal 20a cur- rent source that is switched on or off into the impedance of the set-point divider. when the uvlo threshold is exceeded, the current source is activated to instantly raise the voltage at the uvlo pin. when the uvlo pin falls below the 2.5v threshold, the current source is turned off causing the volt- age at the uvlo pin to fall. the uvlo pin can also be used to implement a remote enable / disable function. by shorting the uvlo pin to ground, the converter can be disabled. the controller can also be disabled through the soft-start pin (ss). the controller will enter a low-power off state if the ss pin is forced below the 0.45v shutdown threshold. buck stage control outputs the LM5041 buck switch maximum duty cycle clamp en- sures that there will be sufficient off time each cycle to recharge the bootstrap capacitor used in the high side gate driver. the buck switch is guaranteed to be off, and the sync switch on, for at least 250ns per switching cycle. the buck stage control outputs (ld and hd) are cmos buffers with logic levels of 0 to 5v. during any fault state or under-voltage off state, the buck stage control outputs will default to hd low and ld high. push-pull outputs the push pull outputs operate continuously at a nominal 50% duty cycle. a distinguishing feature of the LM5041 is the ability to accurately configure either dead time (both-off) or overlap time (both-on) on the complementary push-pull out- puts. the overlap/dead time magnitude is controlled by a resistor connected to the time pin on the controller. the time pin holds one end of the resistor at 2.5v and the other end of the resistor should be connected to either ref for dead time control setting or to gnd for overlap control. the polarity of the current in the time is detected by the LM5041 the magnitude of the overlap/dead time can be calculated as follows: overlap time (ns) = (3.66 x r set )+7 overlap time in ns, r set connected to gnd, r set in k ? dead time (ns) = (3.69 x r set )+21 dead time in ns, r set connected to ref, r set in k ? recommended r set programming range: 10k ? to 100k ? current-fed designs require a period of overlap to insure there is a continuous path for the buck inductor current. voltage-fed designs require a period of dead time to insure there is no time when the push-pull transformer acts as a shorted turn to the low impedance sourcing node. the push- pull outputs alternate continuously under all conditions pro- vided ref the voltage is greater than 3v. LM5041 www.national.com 10
push-pull outputs (continued) 20074904 pwm comparator the pwm comparator compares the slope compensated current ramp signal to the loop error voltage from the internal error amplifier (comp pin). this comparator is optimized for speed in order to achieve minimum controllable duty cycles. the comparator polarity is such that 0v on the comp pin will produce zero duty cycle in the buck stage. error amplifier an internal high gain wide-bandwidth error amplifier is pro- vided within the LM5041. the amplifier?s non-inverting input is tied to a 0.75v reference. the inverting input is connected to the fb pin. in non-isolated applications the power con- verter output is connected to the fb pin via the voltage setting resistors. loop compensation components are con- nected between the comp and fb pins. for most isolated applications the error amplifier function is implemented on the secondary side of the converter and the internal error amp is not used. the internal error amplifier is configured as an open drain output and can be disabled by connecting the fb pin to ground. an internal 5k ? pull-up resistor between the 5v reference and comp can be used as the pull-up for an opto-coupler in isolated applications. current limit/current sense the LM5041 contains two levels of over-current protection. if the voltage at the cs pin exceeds 0.5v the present buck stage duty cycle is terminated (cycle by cycle current limit). if the voltage at the cs pin overshoots the 0.5v threshold and exceeds 0.6v, then the controller will terminate the present cycle and fully discharge the soft-start capacitor. a small rc filter located near the controller is recommended to filter current sense signals at the cs pin. an internal mosfet discharges the external cs pin for an additional 50ns at the beginning of each cycle to reduce the leading edge spike that occurs when the buck stage mosfet is turned on. the LM5041 current sense and pwm comparators are very fast, and may respond to short duration noise pulses. layout considerations are critical for the current sense filter and sense resistor. the capacitor associated with the cs filter must be placed close to the device and connected directly to the pins of the controller (cs and gnd). if a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor, which should also be located close to the ic. a resistor may be used for current sensing instead of a transformer, located in the push-pull transistor sources, but a low inductance type of resistor is required. when designing with a sense resistor, all of the noise sensitive low power grounds should be connected together around the ic and a single connection should be made to the high current power ground (sense resistor ground point). the second level current sense threshold is intended to protect the power converter by initiating a low duty cycle hick-up mode when abnormally high currents are sensed. if the second level threshold is reached, the soft-start capaci- tor will be discharged and a start-up sequence will com- mence when the soft-start capacitor is determined to be fully discharged. the second level threshold will only be reached when a high dv/dt is present at the current sense pin. the current sense transient must be fast enough to reach the second level threshold before the first threshold detector turns off the buck stage driver. very high current sense dv/dt can occur with a saturated power inductor or shorted load. excessive filtering on the cs pin such as an extremely low value current sense resistor or an inductor that does not saturate with excessive loading, may prevent the second level threshold from being reached. if the second level threshold is never exceeded during an overload condition, the first level current sense will continue cycle by cycle limiting and the output characteristic of the converter will be that of a current source. however, a sustained overload current level can cause excessive temperatures in the power train especially the output rectifiers. oscillator and sync capability the LM5041 oscillator is set by a single external resistor connected between the rt pin and gnd. to set a desired oscillator frequency (f), the necessary rt resistor can be calculated from: LM5041 www.national.com 11
oscillator and sync capability (continued) the buck stage will switch at the oscillator frequency and each push-pull output will switch at half the oscillator fre- quency in a push-pull configuration. the LM5041 can also be synchronized to an external clock. the external clock must have a higher frequency than the free running fre- quency set by the rt resistor. the clock signal should be capacitively coupled into the rt pin with a 100pf capacitor. a peak voltage level greater than 3v is required for detection of the sync pulse. the sync pulse width should be set in the 15 to 150ns range by the external components. the rt resistor is always required, whether the oscillator is free running or externally synchronized. the voltage at the rt pin is internally regulated to 2v. the rt resistor should be located very close to the device and connected directly to the pins of the ic (rt and gnd). slope compensation the pwm comparator compares the current sense signal to the voltage at the comp pin. the output stage of the internal error amplifier generally drives the comp pin. at duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. by adding an additional fixed ramp signal (slope compensation) to the current sense ramp, oscillations can be avoided. the LM5041 integrates this slope compensation by buffering the internal oscillator ramp and summing a current ramp generated by the oscil- lator internally with the current sense signal. additional slope compensation may be provided by increasing the source impedance of the current sense signal. soft-start and shutdown the soft-start feature allows the power converter to gradually reach the initial steady state operating point, thereby reduc- ing start-up stresses and surges. at power on, a 10ua cur- rent is sourced out of the soft-start pin (ss) to charge an external capacitor. the capacitor voltage will ramp up slowly and will limit the maximum duty cycle of the buck stage. in the event of a fault as indicated by v cc under-voltage, line under-voltage or second level current limit, the output driv- ers are disabled and the soft-start capacitor is discharged to ground. when the fault condition is no longer present, a soft-start sequence will begin again and buck stage duty cycle will gradually increase as the soft-start capacitor is charged. the ss pin also serves as an enable input. the controller will enter a low power state if the ss pin is forced below the 0.45v threshold. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated, typically at 165 degrees celsius, the controller is forced into a low-power standby state, disabling the output drivers and the bias regulator. this feature is provided to prevent catastrophic failures from accidental device overheating. LM5041 www.national.com 12
thermal protection (continued) 20074906 figure 1. simplified cascaded half-bridge LM5041 www.national.com 13
application circuit: input 35-80v, output 2.5v, 50a 20074907 LM5041 www.national.com 14
physical dimensions inches (millimeters) unless otherwise noted molded tssop-16 ns package number mtc16 molded tssop-16 ns package number sda16a LM5041 www.national.com 15
notes life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com LM5041 cascaded pwm controller national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the righ t at any time without notice to change said circuitry and specifications.

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